W83176R-735 Datasheet, PDF (5/11 Pages) Winbond – 3 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET

W83176R-735
5.1 Clock Outputs
SYMBOL
CLKC[9:0]
CLKT[9:0]
SDATA *
SCLK *
CLK_INT
NC
FB_OUTT
FB_INT
PIN
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
37
12
13
14, 32, 36
33
35
I/O
FUNCTION
OUT Complementory Clocks of differential pair outputs
OUT True Clocks of differential pair outputs
I/O
IN
IN
NONE
OUT
IN
Serial data of I²C 2-wire control interface
Internal pull-up resistor 120K to Vdd
Serial clock of I²C 2-wire control interface
Internal pull-up resistor 120K to Vdd
True reference clock input, 3.3V tolerant input
Not connected
True Feedback output, dedicated for external feedback.
It switches at the same frequency as the CLK. This
output must be wired to FB_INT.
True Feedback input, provides feedback signal to the
internal PLL for synchronization with CLK_INT to
eliminate phase error.
5.2 Power Pins
SYMBOL
GND
V_DD
AVDD
AGND
PIN
FUNCTION
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
Ground
4, 11, 15, 21, 28,
34, 38, 45
Power Supply 2.5V
16
Analog power supply, 2.5V
17
Analog ground
Publication Release Date: April 13, 2005
-3-
Revision 1.1