W982516AH Datasheet, PDF (6/41 Pages) Winbond – 4M x 4 BANKS x 16BIT SDRAM

W982516AH
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc = 3.3V ± 0.3V, TA = 0° to 70°C; Notes: 5, 6, 7, 8)
PARAMETER
Ref/Active to Ref/Active Command
Period
Active to precharge Command Period
Active to Read/Write Command Delay
Time
Read/Write(a) to Read/Write(b)
Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CL* = 2
CL* = 3
CLK Cycle Time
CL* = 2
CLK High Level Width
CL* = 3
CLK Low Level Width
Access Time from CLK
CL* = 2
Output Data Hold Time
CL* = 3
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK
(Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
*CL = CAS Latency
SYM.
t_RC
-7
(PC133, CL2)
MIN. MAX.
56
-75/75L
(PC133, CL3)
MIN. MAX.
65
t_RAS 40 100000 45 100000
t_RCD 15
20
t_CCD
1
1
t_RP
15
20
t_RRD 15
15
t_WR 7.5
10
7
7.5
t_CK 7.5 1000 10 1000
7 1000 7.5 1000
t_CH 2.5
2.5
t_CL 2.5
2.5
t_AC
5.4
6
5.4
5.4
t_OH
3
3
t_HZ
3
7
3
7.5
t_LZ
0
0
t_SB
0
7
0
7.5
t_T
0.5
10
0.5
10
t_DS 1.5
1.5
t_DH 0.8
0.8
t_AS 1.5
1.5
t_AH 0.8
0.8
t_CKS 1.5
1.5
t_CKH 0.8
0.8
t_CMS 1.5
1.5
t_CMS 0.8
0.8
t_REF
64
64
t_RSC 14
15
-8H
(PC100)
MIN. MAX.
68
48 100000
20
1
20
20
10
8
10 1000
8 1000
3
3
6
6
3
3
8
0
0
8
0.5
10
2
1
2
1
2
1
2
1
64
16
UNIT
nS
Cycle
nS
mS
nS
-6-