W982516AH Datasheet, PDF (36/41 Pages) Winbond – 4M x 4 BANKS x 16BIT SDRAM

W982516AH
Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10 11
(1) Read cycle
( a ) CAS latency =2
Command
Read
BST
DQ
( b )CAS latency = 3
Command
Read
DQ
Q0 Q1 Q2 Q3 Q4
BST
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
Command Write
BST
DQ Q0 Q1 Q2 Q3 Q4
Note: BST represents the Burst stop command
Timing Chart of Burst Stop Cycle (Precharge Command)
In the case of Burst Lenght = 8
(1) Read cycle
0
1
2
3
4
5
6
7
8
9 10 11
( a )CAS latency =2
Command Read
PRCG
DQ
( b )CAS latency = 3
Command
Read
Q0 Q1 Q2 Q3 Q4
PRCG
DDQQ
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
( a ) CAS latency =2
Command
Write
PRCG
tWR
DQM
DQ
D0 D1 D2 D3 D4
( b )CAS latency = 3
Command
Write
PRCG
tWR
DQM
DQ
D0 D1 D2 D3 D4
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