W83L518D_05 Datasheet, PDF (6/25 Pages) Winbond – Integrated Media Reader

W83L518D
4. PIN DESCRIPTION
Note:
INt - 5V TTL level input pin
INtp3 - 3.3V TTL level input pin
INts - 5V TTL level Schmitt-trigger input pin
INtsp3 - 3.3V TTL level Schmitt-trigger input pin
I/O12t - 5V TTL level bi-directional pin with 12 mA drive-sink capability
I/O24t - 5V TTL level bi-directional pin with 24 mA drive-sink capability
I/O16tp3
- 3.3V TTL level bi-directional pin with 16 mA drive-sink capability
O2 - 5V output pin with 2 mA drive-sink capability
O12 - 5V output pin with 12 mA drive-sink capability
O16p3 - 3.3V output pin with 16 mA drive-sink capability
OD12p3
- 3.3V Open-drain output pin with 12 mA sink capability.
4.1 Bus Interface
SYMBOL
PME#
RESET#
LFRAME#
LDRQ#
PCICLK
SERIRQ
LAD0
LAD1
LAD2
LAD3
PIN
I/O
FUNCTION
5 OD12p3 Active-low PME event.
4
INtsp3 Active-low system reset signal.
3
INtsp3
Active-low signal indicates start of a new LPC frame or
termination of a premature frame.
2
O16p3 Encoded DMA Request signal.
1
Intsp3 PCI clock input of 33 MHz.
48 I/O16tp3 Serial IRQ input/output.
This signal combining with other LADx signals communicate
47 I/O16tp3 address, control, and data information over the LPC bus between
a host and a peripheral.
This signal combining with other LADx signals communicate
46 I/O16tp3 address, control, and data information over the LPC bus between
a host and a peripheral.
This signal combining with other LADx signals communicate
45 I/O16tp3 address, control, and data information over the LPC bus between
a host and a peripheral.
This signal combining with other LADx signals communicate
44 I/O16tp3 address, control, and data information over the LPC bus between
a host and peripherals.
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