W83194BR-730_05 Datasheet, PDF (6/16 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194BR-730
5. FREQUENCY SELECTION BY HARDWARE
FS3 FS2 FS1 FS0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VCO
(MHZ)
400
400
300
400
336
500
372
400
400
300
333
330
332
360
192
192
CPU
(MHZ)
100
100
100
100
112
125
124
133
133
150
111
110
166
90
48
45
SDRAM
(MHZ)
100
133
150
66.6
112
100
124
100
133
150
166
165
166
90
48
60
PCI
(MHZ)
33.3
33.3
30.0
33.3
33.6
31.3
31
33.3
33.3
30
33.3
33.0
33.3
30
32
30
AGPSEL=0
(MHZ)
66.6
66.6
60
66.6
67.2
62.5
62
66.6
66.6
60
66.6
66
66.6
60
64
60
AGPSEL=1
(MHZ)
50
50
50
50
56
50
46.5
50
50
50
55.6
55
55.6
45
48
45
6. SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the default state at
true power up. "Command Code" byte and "Byte Count" byte must be sent following the
acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't
care", they must be sent and will be acknowledge. After that, the sequence described below
(Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
Bytes sequence order for I²C controller :
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when Read back”, the data sequence is as follows :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4...
until Stop
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