W83194BR-730_05 Datasheet, PDF (1/16 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194BR-730
166MHZ CLOCK FOR SIS CHIPSET
Table of Content-
1. GENERAL DESCRIPTION .............................................................................................................. 2
2. PRODUCT FEATURES................................................................................................................... 2
3. PIN CONFIGURATION.................................................................................................................... 3
4. PIN DESCRIPTION ......................................................................................................................... 3
4.1 Crystal I/O.............................................................................................................................. 3
4.2 CPU, SDRAM, PCI, AGP Clock Outputs .............................................................................. 4
4.3 I²C Control Interface .............................................................................................................. 5
4.4 Fixed Frequency Outputs ...................................................................................................... 5
4.5 Power Pins ............................................................................................................................ 5
5. FREQUENCY SELECTION BY HARDWARE................................................................................. 6
6. SERIAL CONTROL REGISTERS ................................................................................................... 6
6.1 Register 0: Frequency Select Register ................................................................................. 9
6.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)................................................... 9
6.3 Register 2: PCI, AGP Clock Register (1 = Active, 0 = Inactive)............................................ 9
6.4 Register 3: SDRAM Clock Additional Register (1 = Active, 0 = Inactive) ........................... 10
6.5 Register 4: SDRAM Clock Additional Register (1 = Active, 0 = Inactive) ........................... 10
6.6 Register 5: Skew Register................................................................................................... 10
6.7 Register 6: Watchdog Timer Register ................................................................................. 11
6.8 Register 7: M/N Program Register and Divisor ................................................................... 11
6.9 Register 8: M/N Program Register ...................................................................................... 11
6.10 Register 9: Spread Spectrum Register ............................................................................... 12
6.11 Register 10: Divisor Register............................................................................................... 12
6.12 Register 11: Winbond Chip ID Register (Read Only)......................................................... 12
6.13 Register 12: Winbond Chip ID Register (Read Only)......................................................... 13
7. ORDERING INFORMATION ......................................................................................................... 14
8. HOW TO READ THE TOP MARKING .......................................................................................... 14
9. PACKAGE DRAWING AND DIMENSIONS .................................................................................. 15
10. REVISION HISTORY..................................................................................................................... 16
Publication Release Date: May 18, 2005
-1-
Revision 1.0