W83194BR-730_05 Datasheet, PDF (5/16 Pages) Winbond – 166MHZ CLOCK FOR SIS CHIPSET

W83194BR-730
4.3 I²C Control Interface
SYMBOL
PIN
SDATA*
23
SDCLK*
24
I/O
FUNCTION
I/O Serial data of I²C 2-wire control interface
IN Serial clock of I²C 2-wire control interface
4.4 Fixed Frequency Outputs
SYMBOL
PIN
REF0 ^/ &AGPSEL
2
REF1 ^/ &FS3
3
24_48MHz / &Mode
21
48MHz / &FS0
20
I/O
FUNCTION
14.318MHz reference clock. This REF output is
I/O
the atched input for &AGPSEL at initial power up
for H/W selecting the output frequency of AGP
clocks.
14.318MHz reference clock.
I/O ^{Latched input for FS3 at initial power up for H/W}
selecting the output frequency of CPU, SDRAM
and PCI clocks.
24_48MHz output clock, selected by pin16.
Latched Input. &Mode=0, Pin 27,28,30,31 are
I/O _{SDRAM clocks; &Mode=0, Pin27,28,29,31 are}
CPU_STOP#, SDRAM_STOP#,
PCI_STOP#,PD#
48MHz output for USB during normal operation.
I/O ^{Latched input for FS0 at initial power up for H/W}
selecting the output frequency of CPU, SDRAM
and PCI clocks.
4.5 Power Pins
SYMBOL
VddR
VddAGP
VddLCPU
VddP
VddSD
Vdd48
Vss
PIN
1
15
48
7
43,35,29,25
19
4,14,18,19,29,32,3
9,44
FUNCTION
Power supply for Ref [0:1] crystal and core logic.
Power supply for AGP output, 3.3V.
Power supply for CPUC0,T0,CS_C1, either 2.5V or
3.3V.
Power supply for PCICLK[0:5], 3.3V.
Power supply for SDRAM[0:12], and CPU PLL core,
nominal 3.3V.
Power for 24 & 48MHz output buffers and fixed PLL
core.
Circuit Ground.
Publication Release Date:May 18, 2005
-5-
Revision 1.0