W536030T Datasheet, PDF (6/16 Pages) Winbond – VOICE/MELODY/LCD CONTROLLER

W536030T/060T/090T/120T
4. PAD DESCRIPTION
SYMBOL
I/O
FUNCTION
XIN/RXIN
Input pad for main clock oscillator. It can be connected to crystal when
crystal mode is selected (SCR0.2 = 1), otherwise connect a resistor to
I
V_DD to generate main system clock while Ring mode is selected
(SCR0.2 = 0 and default). Oscillator can be enabled or stopped by set
SCR0.1 to 1 or clear to 0 separately. External capacitor connects to
start oscillation and get more accurate clock when crystal mode
XOUT
Output pad for oscillator which is connected to another crystal pad
O when in crystal mode. External capacitor connects to start oscillation
when in crystal mode.
X32I/RSUB1
32.768 KHz crystal input pad or external resistor node 1 by mask
I option. External 15~20pF capacitor connects to start oscillation and
get more accurate clock when in crystal mode.
X32O/RSUB2
32.768 KHz crystal output pad or external resistor node 2 by mask
O option. External 15~20pF capacitor connects to start oscillation when
in crystal mode.
General Input/Output port specified by PM1 register. If output mode is
RA0 ~ RA3/TONE
selected, PM0 register bit 0 can be used to specify CMOS/NMOS
I/O driving capability option. Initial state is input mode. RA3 may be uses
(8)
as TONE if bit 0 of MR0 special register is set to logic 1. An interrupt
source.
RB0 ~ RB3
(8)
General Input/Output port specified by PM2 register. If output mode is
I/O
selected, PM0 register bit 1 can be used to specify CMOS/NMOS
driving capability option. Initial state is input mode (W536090T
/W536120T only.)
RC0 ~ RC3
4-bit schmitter input with internal pull high option specified by PM3
register bit 2. Each pad has an independent interrupt capability
I specified by PEFL special register. Interrupt and STOP mode wake up
source. RC0 is also the external event counter source of Timer1.
(W536060T/090T/120T only.)
RD0
RD1/CLK
RD2/DATA
RD3/ADDR
(4)
4-bit schmitter input port with internal pull high option specified by PM3
register bit 3. Each pad has an independent interrupt capability
I
specified by PEFH special register. Interrupt and STOP mode wake up
source. RD1~3 will be shared as the external memory W55XXX
interface pads while RD port shared as serial bus mask option is
enabled @W536030T/060T.
RE0~RE3
(8)
O
Output port only. PM3 register bit 0 can be used to specify
CMOS/NMOS driving capability option. (W536090T/120T only)
RF0~RF3
(8)
O
Output port only. PM3 register bit 1 can be used to specify
CMOS/NMOS driving capability option. (W536090T/120T only)
RES
I System reset pad, active low with internal pull-high resistor.
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