W39V040FB Datasheet, PDF (6/33 Pages) Winbond – 512K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V040FB
6.5 Sector Erase Command
Sector erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the
"set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The
Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C
in programmer mode, while the command (30H) is latched on the rising edge of #WE.
Sector erase does not require the user to program the device prior to erase. When erasing a Sector,
the remaining unselected sectors are not affected. The system is not required to provide any controls
or timings during these operations.
The automatic Sector erase begins after the erase command is completed, right from the rising edge
of the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7,
Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed
at an address within any of the sectors being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
6.6 Program Operation
The W39V040FB is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte-
program command is entered. The internal program timer will automatically time-out (12µS typ. - TBP)
once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.
6.7 Hardware Data Protection
The integrity of the data stored in the W39V040FB is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 5 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 2.0V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
6.8 WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6,
and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase
operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY
in programmer mode, to determine whether an Embedded Program or Erase operation is in progress
or has been completed.
DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in
progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the
command sequence.
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