W39V040FB Datasheet, PDF (27/33 Pages) Winbond – 512K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE

Timing Waveforms for FWH Interface Mode, continued
13.4 #DATA Polling Timing Diagram
W39V040FB
CLK
#RESET
FWH4
FWH[3:0]
CLK
#RESET
FWH4
FWH[3:0]
CLK
#RESET
FWH4
FWH[3:0]
Start IDSEL
1110b 0000b
1 Clock 1 Clock
XXXXb
Address
M Size
Data
TAR
Sync
TAR
Next Start
XXXXb
An[18:16] An[15:12] An[11:8]
An[7:4]
An[3:0]
0000b Dn[3:0] Dn[7:4] 1111b Tri-State 0000b 1111b Tri-State
Load Address "An" in 7 Clocks
Load Data "Dn"
in 2 Clocks
2 Clocks
Write the last command(program or erase) to the device in FWH mode.
1 Clock
2 Clocks
1 Clock
XXXXb
Start IDSEL
1101b 0000b
1 Clock 1 Clock
XXXXb
Address
M Size
TAR
Sync
Data
TAR
Next Start
XXXXb An[18:16] An[15:12] An[11:8]
An[7:4]
An[3:0]
0000b 1111b Tri-State 0000b XXXXb Dn7,xxx 1111b Tri-State
Load Address in 7 Clocks
2 Clocks 1 Clock Data out 2 Clocks 2 Clocks
1 Clock
Read the DQ7 to see if the internal write complete or not.
Start IDSEL
1101b 0000b
1 Clock 1 Clock
XXXXb
Address
M Size
TAR
Sync
Data
TAR
Next Start
XXXXb An[18:16] An[15:12] An[11:8]
An[7:4]
Load Address in 7 Clocks
An[3:0]
0000b 1111b Tri-State 0000b XXXXb Dn7,xxx 1111b Tri-State
2 Clocks 1 Clock Data out 2 Clocks 2 Clocks
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
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Publication Release Date: April 14, 2005
Revision A3