W39V040FB Datasheet, PDF (25/33 Pages) Winbond – 512K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V040FB
13. TIMING WAVEFORMS FOR FWH INTERFACE MODE
13.1 Read Cycle Timing Diagram
TCYC
CLK
#RESET
TSU THD
FWH4
FWH[3:0]
Start
FWH IDSEL
Read
1101b 0000b
1 Clock 1 Clock
TSU THD
Address
XXXXb XA[22]XXb A[18:16] A[15:12] A[11:8] A[7:4] A[3:0]
Load Address in 7
Clocks
TKQ
M Size
TAR
Sync
0000b 1111b Tri-State 0000b
Data
TAR
Next Start
D[3:0] D[7:4] 1111b Tri-State 0000b
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks 1 Clock
Note: When A22 = high, the host will read the BIOS code from the FWH device.
While A22 = low, the host will read the GPI (Add = FFBC0100) or
Product ID (Add = FFBC0000/FFBC0001) from the FWH device
13.2 Write Cycle Timing Diagram
CLK
#RESET
FWH4
FWH[3:0]
TCYC
Start
FWH
Write
IDSEL
1110b 0000b
Address
XXXXb XXXXb A[18:16] A[15:12] A[11:8]
1 Clock 1 Clock
Load Address in 7 Clocks
A[7:4]
A[3:0]
TSU THD
M Size
Data
TAR
Sync
0000b D[3:0] D[7:4] 1111b Tri-State 0000b
Load Data in 2 Clocks 2 Clocks
1 Clock
TAR
Next Start
1111b Tri-State 0000b
2 Clocks
1 Clock
- 25 -
Publication Release Date: April 14, 2005
Revision A3