W26L010A Datasheet, PDF (6/10 Pages) Winbond – 64K X 16 High Speed CMOS Static RAM

W26L010A
Timing Waveforms
Read Cycle 1
(Address Controlled, CS = OE = UB = LB = VIL, WE = VIH)
Address
D_OUT
TRC
TOH ^TAA
TOH
Read Cycle 2
(Chip Select Controlled, OE = VIL, WE = VIH)
TRC
Address
CS
OE
UB / LB
D_OUT
T_ACS
T_CLZ
TOLZ
TOE
TBA
HIGH-Z
TBLZ
Notes:
1. WE is high for read cycle.
2. Device is continuously selected.
CS = OE = LB = Low
CS = OE = LB = Low
3. Address valid prior to or coincident with CS transition low.
TCHZ
TOHZ
TBHZ
HIGH-Z
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