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W9751G8KB Datasheet, PDF (51/87 Pages) Winbond – 16M x 4 BANKS 꼌 8 BIT DDR2 SDRAM | |||
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W9751G8KB
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
PARAMETER
Clock period jitter
SYMBOL
tJIT(per)
DDR2-667
MIN. MAX.
-125 125
DDR2-800
MIN. MAX.
-100 100
DDR2-1066
MIN. MAX.
-90
90
UNIT
pS
Clock period jitter during DLL locking period
tJIT(per,lck)
-100 100 -80
80
-80
80
pS
Cycle to cycle clock period
tJIT(cc)
-250 250 -200 200 -180 180 pS
Cycle to cycle clock period jitter during DLL
locking period
tJIT(cc,lck)
-200 200 -160 160 -160 160 pS
Cumulative error across 2 cycles
tERR(2per)
-175 175 -150 150 -132 132 pS
Cumulative error across 3 cycles
tERR(3per)
-225 225 -175 175 -157 157 pS
Cumulative error across 4 cycles
tERR(4per)
-250 250 -200 200 -175 175 pS
Cumulative error across 5 cycles
tERR(5per)
-250 250 -200 200 -188 188 pS
Cumulative error across n cycles,
n = 6 ... 10, inclusive
Cumulative error across n cycles,
n = 11 ... 50, inclusive
Duty cycle jitter
tERR(6-10per) -350 350 -300 300 -250 250 pS
tERR(11-50per) -450 450 -450 450 -425 425 pS
tJIT(duty)
-125 125 -100 100 -75
75
pS
Definitions:
- tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
ï¥ï© N
ï¹
tCK(avg) = ïª tCK j ïº / N
ï« j ï½1
ï»
where N = 200
- tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
ï©N
ï¹
ï¥ tCH(avg) = ïª tCH j ïº / (N à tCK(avg))
ï« j ï½1
ï»
where N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
ï©N
ï¹
ï¥ tCL(avg) = ïª tCLj ïº / (N à tCK(avg))
ï« j ï½1
ï»
where N = 200
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Publication Release Date: Feb. 15, 2012
Revision A01
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