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W971GG8JB_12 Datasheet, PDF (51/87 Pages) Winbond – 16M x 8 BANKS x 8 BIT DDR2 SDRAM | |||
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W971GG8JB
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
PARAMETER
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period
Cycle to cycle clock period jitter during DLL
locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles,
n = 6 ... 10, inclusive
Cumulative error across n cycles,
n = 11 ... 50, inclusive
Duty cycle jitter
SYMBOL
tJIT(per)
tJIT(per,lck)
tJIT(cc)
tJIT(cc,lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-10per)
tERR(11-50per)
tJIT(duty)
DDR2-667
MIN. MAX.
-125 125
-100 100
-250 250
-200 200
-175 175
-225 225
-250 250
-250 250
-350 350
-450 450
-125 125
DDR2-800
MIN. MAX.
-100 100
-80
80
-200 200
-160 160
-150 150
-175 175
-200 200
-200 200
-300 300
-450 450
-100 100
DDR2-1066
MIN. MAX.
-90
90
-80
80
-180 180
-160 160
UNIT
pS
pS
pS
pS
-132 132 pS
-157 157 pS
-175 175 pS
-188 188 pS
-250 250 pS
-425 425 pS
-75
75
pS
Definitions:
- tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
ï¥ï© N
ï¹
tCK(avg) = ïª tCK j ïº / N
ï« j ï½1
ï»
where N = 200
- tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
ï¥ï© N
ï¹
tCH(avg) = ïª tCH j ïº / (N à tCK(avg))
ï« j ï½1
ï»
where N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
ï¥ï© N
ï¹
tCL(avg) = ïª tCL j ïº / (N à tCK(avg))
ï« j ï½1
ï»
where N = 200
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Publication Release Date: Jun. 15, 2012
Revision A02
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