W971GG8JB_12 Datasheet, PDF (31/87 Pages) Winbond – 16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB
9. OPERATION MODE
9.1 Command Truth Table
CKE
BA2 A13
COMMAND
Previous Current BA1
A12
A10 A9-A0 CS RAS CAS _{W E} NOTES
Cycle
Cycle BA0 A11
Bank Activate
H
H
BA
Row Address
L
L
H
H
1,2
Single Bank
Precharge
H
H
BA
X
L
X
L
L
H
L
1,2
Precharge All
Banks
H
H
X
X
H
X
L
L
H
L
1
Write
H
H
BA Column L Column L
H
L
L
1,2,3
Write with Auto-
precharge
H
H
BA Column H Column L
H
L
L
1,2,3
Read
H
H
BA Column L Column L
H
L
H
1,2,3
Read with Auto-
precharge
H
H
BA Column H Column L
H
L
H
1,2,3
(Extended)
Mode Register
H
Set
H
BA
OP Code
L
L
L
L
1,2
No Operation
H
X
X
X
X
X
L
H
H
H
1
Device Deselect
H
Refresh
H
Self Refresh
Entry
H
Self Refresh Exit
L
Power Down
Mode Entry
H
X
X
X
X
X
H
X
X
X
1
H
X
X
X
X
L
L
L
H
1
L
X
X
X
X
L
L
L
H
1,4
H
X
X
X
H
X
X
X
X
1,4,5
L
H
H
H
H
X
X
X
L
X
X
X
X
1,6
L
H
H
H
Power Down
Mode Exit
L
H
X
X
X
H
X
X
X
X
1,6
L
H
H
H
Notes:
1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA [2:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See “Burst Interrupt” in section 8.5 for details.
4. V_REF must be maintained during Self Refresh operation.
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 8.9.
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Publication Release Date: Jun. 15, 2012
Revision A02