W9864G2JH_13 Datasheet, PDF (5/43 Pages) Winbond – 512K x 4 BANKS x 32BITS SDRAM

W9864G2JH
5. PIN DESCRIPTION
PIN NUMBER
24, 25, 26, 27, 60, 61, 62,
63, 64, 65, 66
22, 23
2, 4, 5, 7, 8, 10, 11, 13, 31,
33, 34, 36, 37, 39, 40, 42,
45, 47, 48, 50, 51, 53, 54,
56, 74, 76, 77, 79, 80, 82,
83, 85
20
19
18
PIN NAME
A0A10
BS0, BS1
FUNCTION
Address
Bank Select
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0A10. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
DQ0DQ31
Data
Multiplexed pins for data output and input.
Input/ Output
CS
RAS
CAS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising
Row Address
Strobe
edge of the clock RAS , CAS and WE define
the operation to be executed.
Column Address
Strobe
Referred to RAS
17
WE
Write Enable _{Referred to RAS}
16, 28, 59, 71
DQM0DQM3
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency
of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the
write operation with zero latency.
68
CLK
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and
67
CKE
Clock Enable
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
1, 15, 29, 43
VDD
Power
Power for input buffers and logic circuit inside
DRAM.
44, 58, 72, 86
VSS
Ground
Ground for input buffers and logic circuit inside
DRAM.
3, 9, 35, 41, 49, 55, 75, 81
VDDQ
Power for I/O Separated power from VDD, to improve DQ
Buffer
noise immunity.
6, 12, 32, 38, 46, 52, 78, 84
VSSQ
Ground for I/O Separated ground from VSS, to improve DQ
Buffer
noise immunity.
14, 21, 30, 57, 69, 70, 73
NC
No Connection No connection.
Publication Release Date: Oct. 07, 2013
-5-
Revision A02