W9864G2JH_13 Datasheet, PDF (16/43 Pages) Winbond – 512K x 4 BANKS x 32BITS SDRAM

W9864G2JH
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V ± 0.3V for-5/-6, VDD = 2.7V~3.6V for -7 on TA = 0 to 70°C)
(VDD = 3.3V ± 0.3V for-6I/-6A, TA = -40 to 85°C)
(VDD = 3.3V ± 0.3V for-6K, TA / TCASE = -40 to 105°C)(Notes: 5, 6)
PARAMETER
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b) Command
Period
SYM.
t_RC
t_RAS
t_RCD
t_CCD
-5
-6/-6I/-6A/-6K
-7
MIN. MAX. MIN. MAX. MIN. MAX.
UNIT NOTES
55
60
65
40 100000 42 100000 45 100000 nS
15
18
20
1
1
1
t_CK
Precharge to Active Command Period
t_RP
15
18
20
nS
Active(a) to Active(b) Command Period
t_RRD 10
12
14
CL* = 2
2
2
2
Write Recovery Time
CL* = 3
t_WR
2
2
2
t_CK
CLK Cycle Time
CL* = 2
CL* = 3
10 1000 7.5 1000 10 1000
t_CK
5 1000 6 1000 7 1000
CLK High Level width
t_CH
2
2
2
8
CLK Low Level width
t_CL
2
2
2
8
CL* = 2
6
5.5
6
Access Time from CLK
CL* = 3
t_AC
4.5
5
5.5
9
Output Data Hold Time
t_OH
3
3
3
9
Output Data High
Impedance Time
CL* = 2
6
6
6
CL* = 3
t_HZ
4.5
5
5.5
7
Output Data Low Impedance Time
Power Down Mode Entry Time
t_LZ
0
0
0
9
t_SB
0
5
0
6
0
7
nS
Transition Time of CLK (Rise and Fall)
t_T
1
1
1
Data-in Set-up Time
t_DS 1.5
1.5
1.5
8
Data-in Hold Time
t_DH 1.0
1.0
1.0
8
Address Set-up Time
t_AS 1.5
1.5
1.5
8
Address Hold Time
t_AH 1.0
1.0
1.0
8
CKE Set-up Time
t_CKS 1.5
1.5
1.5
8
CKE Hold Time
t_CKH 1.0
1.0
1.0
8
Command Set-up Time
t_CMS 1.5
1.5
1.5
8
Command Hold Time
t_CMH 1.0
1.0
1.0
8
Refresh Time
-40°C ≤ TA / TCASE ≤ 85°C t_REF
64
64
64
mS
(4K/Refresh Cycles) 85°C < TA / TCASE ≤ 105°C t_REFA
--
16
--
Mode register Set Cycle Time
t_RSC
2
2
2
t_CK
Exit self refresh to ACTIVE command
t_XSR
70
72
75
nS
*CL = CAS Latency
* -- = not support
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Publication Release Date: Oct. 07, 2013
Revision A02