W77IE58_06 Datasheet, PDF (47/82 Pages) Winbond – 8-BIT MICROCONTROLLER

W77IE58/W77I058A
Table 6. SFR Reset Value, continued
SFR NAME
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P1
SCON
SBUF
P2
SADDR1
SCON1
ROMMAP
EXIF
P4
RESET VALUE
00000000b
00000000b
00xx0000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000001b
11111111b
00000000b
xxxxxxxxb
11111111b
00000000b
00000000b
01xxx110b
0000xxx0b
xxxx1111b
SFR NAME
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
TA
PSW
WDCON
ACC
EIE
B
EIP
PC
SADEN1
SBUF1
PMR
STATUS
RESET VALUE
00000000b
00000x00b
00000000b
00000000b
00000000b
00000000b
11111111b
00000000b
0x0x0xx0b
00000000b
xxx00000b
00000000b
xxx00000b
00000000b
00000000b
xxxxxxxxb
010xx0x0b
000x0000b
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
Watchdog reset
Power on reset
WDCON
0x0x0xx0b
0x0x01x0b
01000000b
The POR bit WDCON.6 is set only by the power on reset. The PFI bit WDCON.4 is set when the
power fail condition occurs. However, a power-on reset will clear this bit. The WTRF bit WDCON.2 is
set when the Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit
WDCON.1 is cleared by power on resets. This disables the Watchdog timer resets. A watchdog or
external reset does not affect the EWT bit.
INTERRUPTS
The W77I058 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can
be globally enabled or disabled.
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Publication Release Date: November 10, 2006
Revision A7