W77IE58_06 Datasheet, PDF (43/82 Pages) Winbond – 8-BIT MICROCONTROLLER

W77IE58/W77I058A
Wait State Control Signal
Either with the software using stretch value to change the required machine cycle of MOVX
instruction, the W77I058 provides another hardware signal WAIT to implement the wider duration of
external data access timing. This wait state control signal is the alternate function of P4.0 such that it
can only be invoked to 44-pin PLCC/QFP package type. The wait state control signal can be enabled
by setting WS (ROMMAP.7) bit. When enabled, the setting of stretch value decides the minimum
length of MOVX instruction cycle and the device will sample the WAIT pin at each C3 state before
the rising edge of read/write strobe signal during MOVX instruction. Once this signal being
recongnized, one more machine cycle (wait state cycle) will be inserted into next cycle. The inserted
wait state cycles are unlimited, so the MOVX instruction cycle will end in which the wait state control
signal is deactivated. Using wait state control signal allows a dynamically access timimg to a selected
external peripheral. The WS bit is accessed by the Timed Access Protection procedure.
Set WS bit and stretch value = 0 to control wait signal.
6.3 Power Management
The W77I058 has several features that help the user to control the power consumption of the device.
The power saving features are basically the POWER DOWN mode, ECONOMY mode and the IDLE
mode of operation.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial port
blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program
Status Word, the Accumulator and the other registers hold their contents. The ALE and PSEN pins are
held high during the Idle state. The port pins hold the logical states they had at the time Idle was
activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the
activation of any enabled interrupt can wake up the processor. This will automatically clear the Idle bit,
terminate the Idle mode, and the Interrupt Service Routine(ISR) will be executed. After the ISR,
execution of the program will continue from the instruction which put the device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either by
applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The
external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the W77I058 is exiting from an Idle mode with a reset, the instruction following the one which
put the device into Idle mode is not executed. So there is no danger of unexpected writes.
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Publication Release Date: November 10, 2006
Revision A7