W77IE58_06 Datasheet, PDF (27/82 Pages) Winbond – 8-BIT MICROCONTROLLER

W77IE58/W77I058A
B Register
Bit:
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
Mnemonic: B
Address: F0h
B.7-0: The B register is the standard 8052 register that serves as a second accumulator.
Exterded Interrupt Priority
Bit:
7
6
5
4
3
2
1
0
-
-
-
PWDI PX5 PX4 PX3 PX2
Mnemonic: EIP
Address: F8h
EIP.7-5: Reserved bits.
PWDI: Watchdog timer interrupt priority.
PX5: External Interrupt 5 Priority. 0 = Low priority, 1 = High priority.
PX4: External Interrupt 4 Priority. 0 = Low priority, 1 = High priority.
PX3: External Interrupt 3 Priority. 0 = Low priority, 1 = High priority.
PX2: External Interrupt 2 Priority. 0 = Low priority, 1 = High priority.
6.1 Instruction
The W77I058 executes all the instructions of the standard 8032 family. The operation of these
instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of
these instructions is different. The reason for this is two fold. Firstly, in the W77I058, each machine
cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the
W77I058 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8032
there can be two fetches per machine cycle, which works out to 6 clocks per fetch.
The advantage the W77I058 has is that since there is only one fetch per machine cycle, the number of
machine cycles in most cases is equal to the number of operands that the instruction has. In case of
jumps and calls there will be an additional cycle that will be needed to calculate the new address. But
overall the W77I058 reduces the number of dummy fetches and wasted cycles, thereby improving
efficiency as compared to the standard 8032.
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Publication Release Date: November 10, 2006
Revision A7