W25Q32V Datasheet, PDF (45/61 Pages) Winbond – 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q32V
10.2.28 Continuous Read Mode Reset (FFh or FFFFh)
For Fast Read Dual/Quad I/O operations, “Continuous Read Mode” Bits (M7-0) are implemented to
further reduce instruction overhead. By setting the (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O
operation does not require the BBh/EBh instruction code (See 10.2.12 Fast Read Dual I/O and 10.2.13
Fast Read Quad I/O for detail descriptions).
If the system controller is Reset during operation it will likely send a standard SPI instruction, such
as Read ID (9Fh) or Fast Read (0Bh), to the W25Q32. However, as with most SPI Serial Flash
memories, the W25Q32V does not have a hardware Reset pin, so if Continuous Read Mode bits are set
to “Ax” hex, the 25Q16 will not recognize any standard SPI instructions. To address this possibility, it is
recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system
Reset. Doing so will release the Continuous Read Mode from the “Ax” hex state and allow Standard SPI
instructions to be recognized. The Continuous Read Mode Reset instruction is shown in figure 28.
/CS
CLK
IO₀
IO₁
IO₂
IO₃
Mode 3
Mode 0
Mode Bit Reset
for Quad I/O
Mode Bit Reset
for Dual I/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Mode 3
Mode 0
FFh
FFh
Don’t Care
Don’t Care
Don’t Care
Figure 28. Continuous Read Mode Reset for Fast Read Dual/Quad I/O
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are
needed to shift in instruction “FFFFh”.
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Publication Release Date: August 19, 2009
Preliminary - Revision E