W986408CH Datasheet, PDF (40/44 Pages) Winbond – 2M x 8BIT x 4 BANKS SDRAM

W986408CH
2M x 8 bit x 4 Banks SDRAM
Timing chart of Burst Stop cycle ( Precharge Command )
In the case of Burst Lenght = 8
(1) Read cycle
0
1
2
3
4
5
6
7
8
9
( a )CAS latency =2
Command _Read
PRCG
DQ
( b )CAS latency = 3
Command
Read
Q0 Q1 Q2 Q3 Q4
PRCG
DDQQ
( c )CAS latency = 4
Command
Read
Q0 Q1 Q2 Q3 Q4
PRCG
DQ
(2) Write cycle
Q0 Q1 Q2 Q3 Q4
( a ) CAS latency =2
Command
DQM
Write
PRCG
tWR
DQ
D0 D1 D2 D3 D4
( b )CAS latency = 3
Command
DQM
Write
PRCG
tWR
DQ
D0 D1 D2 D3 D4
( c )CAS latency = 4
Command _Write
PRCG
tWR
DQM
DQ
D0 D1 D2 D3 D4
10 11
Note ) PRCG represents the Precharge command
Revision 1.0
- 40 -
Publication Release Date: March, 1999