W986408CH Datasheet, PDF (37/44 Pages) Winbond – 2M x 8BIT x 4 BANKS SDRAM

W986408CH
Timing Chart of Read to Write cycle
In the case of Burst Length=4
2M x 8 bit x 4 Banks SDRAM
01
2
3
4
5
6
7
8
9
10 11
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0 D1 D2 D3
( b ) Command
DQM
DQ
Read
Write
D0 D1 D2 D3
(2) CAS Latency=3
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Read Write
D0 D1 D2 D3
Read
Write
D0 D1 D2 D3
(3) CAS Latency=4
( a ) Command
DQM
DQ
( b ) Command
DQM
DQ
Read Write
D0 D1 D2 D3
Read
Write
D0 D1 D2 D3
Note ) The Output data must be masked by DQM to avoid I/O conflict
Revision 1.0
- 37 -
Publication Release Date: March, 1999