W986408CH Datasheet, PDF (3/44 Pages) Winbond – 2M x 8BIT x 4 BANKS SDRAM

W986408CH
Pin Assignment
2M x 8 bit x 4 Banks SDRAM
Pin Number Pin Name
23 ~ 26, 22,
29 ~35
A0~ A11
20, 21
BS0, BS1
2, 5, 8, 11,
44, 47, 50, 53
DQ0 ~ DQ7
19
CS#
18
RAS#
17
CAS#
16
WE#
39
DQM
38
CLK
37
CKE
1, 14, 27
28, 41, 54
3, 9, 43, 49
VCC
VSS
VCCQ
6, 12, 46, 52 VSSQ
4, 7, 10, 13,
15, 36, 40, 42, NC
45, 48, 51
Function
Description
Address
Multiplexed pins for row and column address.
Row address : A0 ~ A11. Column address: A0 ~ A8.
Bank Select
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
Chip Select
decoder is disabled, new command is ignored and previous
operation continues.
Row Address
Command input. When sampled at the rising edge of the clock,
Strobe
RAS#, CAS# and WE# define the operation to be executed.
Column Address
Strobe
Referred to RAS#
Write Enable
Referred to RAS#
The output buffer is placed at Hi-Z(with latency of 2) when DQM
input/output mask is sampled high in read cycle. In write cycle, sampling DQM
high will block the write operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE
Clock Enable
is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
Power ( +3.3 V ) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power ( + 3.3 V ) Separated power from VCC, used for output buffers to improve
for I/O buffer
noise.
Ground for I/O
buffer
Separated ground from VSS, used for output buffers to improve
noise.
No Connection No connection
Revision 1.0
Publication Release Date: March, 1999
-3-