W83194R-67A Datasheet, PDF (4/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67A
5.3 I²C Control Interface
SYMBOL
PIN
*SDATA
23
*SDCLK
24
PRELIMINARY
I/O
FUNCTION
I/O Serial data of I²C 2-wire control interface with internal
pull-up resistor.
IN Serial clock of I²C 2-wire control interface with
internal pull-up resistor.
5.4 Fixed Frequency Outputs
SYMBOL
PIN
REF0 / *PCI_STOP#
2
REF1 / *FS2
48
24MHz / *FS1
25
48MHz / *FS0
26
I/O
FUNCTION
I/O 14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input
low (In mobile mode. MODE=0)
I/O 14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
I/O 24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
I/O 48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
5.5 Power Pins
SYMBOL
Vddq1
VddL1
Vddq2
Vddq3
Vddq4
Vss
PIN
FUNCTION
1
Power supply for Ref [0:1] , Xin and Xout crystal.
47
Power supply for CPU clock outputs, either 2.5V or
3.3V.
6, 14
Power supply for PCICLK_F, PCICLK[1:4], 3.3V.
19, 30, 36
Power supply for SDRAM_F,SDRAM[0:11], and PLL
core, nominal 3.3V.
27
Power for 24 & 48MHz output buffers and PLL core.
3,9,16,22,33,40,44 Circuit Ground.
Publication Release Date: Feb. 1999
-4-
Revision 0.30