W83194R-67A Datasheet, PDF (1/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67A
100MHZ 3-DIMM CLOCK FOR VIA MVP4
1.0 GENERAL DESCRIPTION
The W83194R-67A is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67A provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67AA also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194R-67A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping individual
clock outputs and frequency selection through I²C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• Supports Pentium™ , AMD, Cyrix CPU with I²C.
• 4 CPU clocks (one free-running CPU clock)
• 13 SDRAM clocks for 3 DIMs
• 6 PCI synchronous clocks
• Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
• < 250ps skew among CPU and SDRAM clocks
• < 4ns propagation delay SDRAM from buffer input
• Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
• Smooth frequency switch with selections from 60 MHz to 124 MHz CPU
• I²C 2-Wire serial interface and I²C read back
• ¡Ó0.25% or ¡Ó0.5% spread spectrum function to reduce EMI
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 2ms power up clock stable time
• MODE pin for power Management
• One 48 MHz for USB & one 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Feb. 1999
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Revision 0.30