W83194R-67A Datasheet, PDF (2/18 Pages) Winbond – 100MHZ 3-DIMM CLOCK FOR VIA MVP4

W83194R-67A
3.0 BLOCK DIAGRAM
Xin
Xout
BUFFER IN
FS(0:3)* ⁴
MODE*
*CPU_STOP#
*PCI_STOP#
SDATA*
SDCLK*
PLL2
1/2
~
XTAL
OSC
PLL1
Spread
Spectrum
LATCH
~⁴
POR
Control
Logic
Config.
Reg.
STOP
STOP
PCI
Clock STOP
Divider
PRELIMINARY
48MHz
24MHz
REF(0:1)
2
CPUCLK_F
CPUCLK(0:2)
3
SDRAM_F
SDRAM(0:11)
12
PCICLK(0:4)
5
PCICLK_F
4.0 PIN CONFIGURATION
Vddq1
1
* PCI_STOP#/REF0
2
Vss
3
Xin
4
Xout
5
Vddq2
6
PCICLK_F/ *MODE
7
PCICLK0/ *FS3
8
Vss
9
PCICLK1
10
PCICLK2
11
PCICLK3
12
PCICLK4
13
Vddq2
14
BUFFER IN
15
Vss
16
SDRAM11
17
SDRAM10
18
Vddq3
19
SDRAM 9
20
SDRAM 8
21
Vss
22
*SDATA
*SCLK
23
24
48
REF1/ *FS2
47
VddL1
46
CPUCLK_F
45
CPUCLK0
44
Vss
43
CPUCLK1
42
CPUCLK2
41
*CPU_STOP#
40
Vss
39
SDRAM_F
38
SDRAM 0
37
SDRAM 1
36
Vddq3
35
SDRAM 2
34
SDRAM 3
33
Vss
32
SDRAM 4
31
SDRAM 5
30
Vddq3
29
SDRAM 6
28
SDRAM 7
27
Vddq4
26
48MHz/ *FS0
25
24MHz/ *FS1
Publication Release Date: Feb. 1999
-2-
Revision 0.30