W25P240A Datasheet, PDF (4/14 Pages) Winbond – 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

W25P240A
TRUTH TABLE
CYCLE
ADDRESS
USED
CE
ADSP
ADSC
ADV
OE
Unselected
No
1
X
0
X
X
Begin Read
External
0
0
X
X
X
Begin Read
External
0
1
0
X
X
Continue Read
Next
X
1
1
0
1
Continue Read
Next
X
1
1
0
0
Continue Read
Next
1
X
1
0
1
Continue Read
Next
1
X
1
0
0
Suspend Read
Current
X
1
1
1
1
Suspend Read
Current
X
1
1
1
0
Suspend Read
Current
1
X
1
1
1
Suspend Read
Current
1
X
1
1
0
Begin Write
Current
X
1
1
1
X
Begin Write
Current
1
X
1
1
X
Begin Write
External
0
1
0
X
X
Continue Write
Next
X
1
1
0
X
Continue Write
Next
1
X
1
0
X
Suspend Write
Current
X
1
1
1
X
Suspend Write
Current
1
X
1
1
X
DATA
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D-Out
Hi-Z
D-Out
Hi-Z
D-Out
Hi-Z
D-Out
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
WRITE*
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to
the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set up the
SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold
are met.
timings
WRITE TABLE
READ/WRITE FUNCTION
Read
Read
Write byte 1 I/O1−I/O8
Write byte 2 I/O9−I/O16
Write byte 2, byte 1
GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1
1
1
X
X
X
X
X
X
X
X
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
-4-