W25P240A Datasheet, PDF (3/14 Pages) Winbond – 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

W25P240A
PIN DESCRIPTION
SYMBOL
A0−A15
I/O1−I/O64
CLK
CE
GW
BWE
BW1 − BW8
OE
ADV
ADSC
ADSP
VDD
VSS
TYPE
Input, Synchronous
I/O, Synchronous
Input, Clock
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
DESCRIPTION
Host Address
Data Inputs/Outputs
Processor Host Bus Clock
Chip Enables
Global Write
Byte Write Enable from Cache Controller
Host Bus Byte Enables used with BWE
Output Enable Input
Internal Burst Address Counter Advance
Address Status from chip set
Address Status from CPU
Power Supply
Ground
FUNCTIONAL DESCRIPTION
The W25P240A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports only one burst address sequence for Intel™ systems. The burst cycles are
initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low.
Burst Address Sequence
External Start Address
Second Address
Third Address
Fourth Address
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
Publication Release Date: February 1998
-3-
Revision A4