W921E400A Datasheet, PDF (31/53 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E400A/W921C400
6.11.2 Interrupt Enable Flag
When the interrupt is enabled by the event, the program counter will jump to the interrupt address and
the enable interrupt flag (ENINT) bit0 is cleared, at the same time, all the interrupt will be disabled.
The only way to enable the interrupt again is to set the ENINT bit0 or execute the RTNI instruction.
ENINT register: (address = 034H, default data = 0H)
b3
b2
b1
b0
Reserved ^{Reserved Reserved}
0: Disable all interrupt
1: Enable all interrupt
When the interrupt is enabled by the event, the individual interrupt request signal is cleared by the
hardware automatically but the other interrupt request signals will remain the same condition. The
only method of resetting the interrupt request signal is to execute the instruction CLR EVF, #I (I is a
8bits data, for example, CLR EVF, #00000001b instruction implies to clear TM0 interrupt request
signal), it is a 2 words / 2 cycles instruction; the format of the immediate data is shown below.
i7 i6 i5 i4 i3
i2 i1 i0
Reserved
1: TM0 interrupt request signal is cleared
1: TM2 interrupt request signal is cleared
1: TM3 interrupt request signal is cleared
1: INT0 pin interrupt request signal is cleared
1: Serial port interrupt request signal is cleared
1: Comparator interrupt request signal is cleared
1: P4.2 interrupt request signal is cleared
6.12 Operating Mode
There are three types of operating mode in this chip  normal mode, hold mode and stop mode.
6.12.1 Normal Mode:
All functions works well and the µC operates according to the clock generated by the system clock.
6.12.2 Hold Mode:
In hold mode, all operations of µC cease, except for the operation of the oscillator, timer/counter,
serial port and interrupt active pins. The µC enters hold mode when the HOLD instruction is executed.
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Publication Release Date: July 1999
Revision A3