W921E400A Datasheet, PDF (20/53 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E400A/W921C400
SRSPC register: (address = 00BH, default data = 0H)
b3
b2
b1
b0
b3 b2 b1 b0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Input frequency
Reserved
fsys/4 Hz
fsys/8 Hz
fsys/16 Hz
fsys/32 Hz
fsys/64 Hz
fsys/128 Hz
fsys/256 Hz
fsys/512 Hz
fsys/1024 Hz
fsys/2048 Hz
Normally the WCLK or RCLK pin will remain in high state and the serial data will be latched at the
rising edge of the WCLK or RCLK signal, but the serial clock inverter control register (SRINV) will
invert the above function. In this case WCLK or RCLK pin will remain in low state and the serial data
will be latched at the falling edge of the WCLK or RCLK signal.
The transmitting serial clock can come from WCLK or RCLK, depending on which one is enabled. If
the serial function is disabled, it will cause the relative pins to be in high impedance and it will not
affect the contents of serial buffer registers (start at address 050H).
6.7 DTMF Generator
There is one dual tone multi-frequency (DTMF) generator channel in this chip. The correct DTMF
output frequency is decided by the OSCCTR register as shown below.
OSCCTR register: (address = 013H, default data = 0H)
b3
b2
b1
b0
Reserved
b2 b1 b0
000
001
010
011
100
101
Osc. Selection
400 KHz
800 KHz
2 MHz
4 MHz
Reserved
3.58MHz
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