W921E400A Datasheet, PDF (19/53 Pages) Winbond – 4-BIT MICROCONTROLLER

W921E400A/W921C400
SRINV register: (address = 00CH, default data = 0H)
b3
b2
b1
b0
0: Serial data latch at WCLK/RCLK rising edge
(normal high)
1: Serial data latch at WCLK/RCLK falling edge
(normal low)
0: WCLK and RCLK pins work as the internal
clock output pin
1: WCLK and RCLK pins work as the external
clock input pin
0: RCLK and RDATA disable (H-Z)
1: RCLK and RDATA enable
0: WCLK and WDATA disable (H-Z)
1: WCLK and WDATA enable
The serial interface configuration is shown below:
To Port P6 Normal I/O Register
P6.3 P6.2 P6.1 P6.0
Port P6 Pull-High Resisters
VDD
WDATA
WCLK
SRINV.3
RDATA
RCLK
P6IO.0
P6IO.1
SRINV.2
SCLK
P6IO.2
P6IO.3
Clock Source
and Latch
Control Circuit
Serial Clock Speed
Control Circuit
f SYS System
Clock
1/4
High Speed
Clock
SDATA
Serial/Parallel
I/O Buffer
P6PH
To Port P6
Serial Buffer
Registers
050H
14EH
The internal serial clock can be controlled by the serial clock speed control register (SRSPC) and the
format is as follows:
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Publication Release Date: July 1999
Revision A3