W45B012 Datasheet, PDF (3/16 Pages) Winbond – 1M x 1 SERIAL FLASH MEMORY

Preliminary W45B012
FUNCTIONAL DESCRIPTION
Device Operation
The W45B012 uses bus cycles of 8 bits each for commands, data, and addresses to execute
operations. The operation instructions are listed in the table below. All instructions are synchronized off
a high to low transition of #CE. The first low to high transition on SCK will initiate the instruction
sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any
low to high transition on #CE before the input instruction completes will terminate any instruction in
progress and return the device to the standby mode.
Read
The Read operation outputs the data in order from the initial accessed address. While SCK is input,
the address will be incremented automatically until end (top) of the address space, then the internal
address pointer automatically increments to beginning (bottom) of the address space (00000h), and
data out stream will continue. The read data stream is continuous through all addresses until
terminated by a low to high transition on #CE.
Sector/Chip-erase Operation
The Sector-Erase operation clears all bits in the selected sector to "FF". The Chip-Erase instruction
clears all bits in the device to "FF".
Byte-program Operation
The Byte-Program operation programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state ("FF") when initiating a Program operation. The data is input from bit 7
to bit 0 in order.
Software Status Operation
The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a "0" an
Erase or Program operation is in progress, the device is busy. If bit 0 is at a "1" the device is ready for
any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low
to high transition on #CE.
Reset
Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a
high to low transition on the #RESET pin. The device will remain in reset condition as long as #RESET
is low. Minimum reset time is 10 µS. See Figure 14 for reset timing diagram. #RESET is internally
pulled-up and could remain unconnected during normal operation. After reset, the device is in standby
mode, a high to low transition on #CE is required to start the next operation. An internal power-on reset
circuit protects against accidental data writes. Applying a logic level low to #RESET during the power-
on process then changing to a logic level high when VDD has reached the correct voltage level will
provide additional protection against accidental writes during power on.
Read WINBOND ID/Read Device ID
The Read Manufacturer ID and Read Device ID operations read the JEDEC assigned manufacturer
identification and the manufacturer assigned device identification codes. These codes may be used to
determine the actual device resident in the system.
Publication Release Date: April 18, 2002
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Revision A1