W27L01 Datasheet, PDF (3/15 Pages) Winbond – 128K X 8 ELECTRICALLY ERASABLE EPROM

W27L01
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L01 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power dissipation
and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and
transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic
capacitor connected between its VDD and Vss. This high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array's power supply connection between VDD and Vss.
The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
Table of Operating Modes
VDD = 3.3V ±10%, Vpp = VpE = VHH = 12V, VCP = VPE = 5V, X = VIH or VIL
MODE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Program Inhibit
Erase
Erase Verify
Erase Inhibit
Product
Identifier-Manufacturer
Product Identifier-Device
#CE
VIL
VIL
VIH
VDD ±0.3V
VIL
VIL
VIH
VIL
VIL
VIH
#OE
VIL
VIH
X
X
VIH
VIL
X
VIH
VIL
X
#PGM
X
X
X
X
VIL
VIH
X
VIL
VIH
X
PINS
A0 A9
XX
XX
XX
XX
XX
XX
XX
VIL VPE
XX
XX
VDD
VDD
VDD
VDD
VDD
VCP
VCP
VCP
VCP
VPE
VCP
VPP
VDD
VDD
VDD
VDD
VPP
VPP
VPP
VPE
VPP
VPE
OUTPUTS
DOUT
High Z
High Z
High Z
DIN
DOUT
High Z
FF (Hex)
DOUT
High Z
VIL
VIL
X
VIL VHH VDD VDD DA (Hex)
VIL
VIL
X VIH VHH VDD VDD 01 (Hex)
Publication Release Date: February 20, 2003
-3-
Revision A3