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W25Q16V Datasheet, PDF (26/60 Pages) Winbond – 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI | |||
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W25Q16V
10.2.12 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with âContinuous Read Modeâ
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
âContinuous Read Modeâ bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are donât care
(âxâ). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the âContinuous Read Modeâ bits (M7-0) equals âAxâ hex, then the next Fast Read Dual I/O instruction
(after /CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the âContinuous Read Modeâ bits (M7-0) are any value other than
âAxâ hex, the next instruction (after /CS is raised and then lowered) requires the first byte instruction
code, thus returning to normal operation. A âContinuous Read Modeâ Reset instruction can be used to
reset (M7-0) before issuing normal instructions (See 10.2.29 for detailed descriptions).
Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)
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