W39V040C Datasheet, PDF (22/36 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V040C
10.8 Write Cycle Timing Parameters
PARAMETER
Reset Time
Address Setup Time
Address Hold Time
R/#C to Write Enable High Time
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
#OE Hold Time
Byte programming Time
Sector Erase Cycle Time (Note 2)
Page Erase Cycle Time (Note 2)
Program/Erase Valid to RY/#BY Delay
SYMBOL
TRST
TAS
TAH
TCWH
TWP
TWPH
TDS
TDH
TOEH
TBP
TPEC
TPEC2
TBUSY
MIN.
1
50
50
50
100
100
50
50
0
-
-
-
90
TYP.
-
-
-
-
-
-
-
-
-
10
0.6
0.3
-
MAX.
-
-
-
-
-
-
-
-
-
200
6
0.8
-
UNIT
μS
nS
nS
nS
nS
nS
nS
nS
nS
μS
S
S
nS
Notes: 1. All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
2. Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm,
all bytes are programmed to 00H before erasure
10.9 Data Polling and Toggle Bit Timing Parameters
PARAMETER
SYMBOL
W39V040C
MIN. MAX.
#OE to Data Polling Output Delay
TOEP
-
350
#OE to Toggle Bit Output Delay
TOET
-
350
Toggle or Polling interval (for sector erase only) (Note1)
-
50
-
Note1: Minimum timing interval between Toggle-check or Polling-check is required for sector erase only
UNIT
nS
nS
mS
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