W39V040C Datasheet, PDF (12/36 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE

W39V040C
8. TABLE OF OPERATING MODES
8.1 Operating Mode Selection - Programmer Mode
MODE
Read
Write
Standby
Write Inhibit
Output Disable
#OE
VIL
VIH
X
VIL
X
VIH
#WE
VIH
VIL
X
X
VIH
X
#RESET
VIH
VIH
VIL
VIH
VIH
VIH
PINS
ADDRESS
AIN
AIN
X
X
X
X
DQ.
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
8.2 Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "START Cycle" when it is selected. When it
is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "LPC Cycle Definition".
8.3 LPC Cycle Definition
FIELD
Start
Cycle Type & Dir
TAR
Addr.
Sync.
Data
NO. OF
CLOCKS
DESCRIPTION
1
"0000b" appears on LPC bus to indicate the initial
1
"010Xb" indicates memory read cycle; while "011xb" indicates
memory write cycle. "X" mean don't have to care.
2
Turned Around Time
Address Phase for Memory Cycle. LPC supports the 32 bits address
8
protocol. The addresses transfer most significant nibble first and
least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first ,
and Address[3:0] on LAD[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b"
N
means Short Wait, "0110b" means Long Wait, "1001b" for DMA only,
"1010b" means error, other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant
2
nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0]
first, then DQ[7:4] on LAD[3:0] last.)
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