W39V040FB_07 Datasheet, PDF (21/34 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V040FB
Programmer Interface Mode AC Characteristics, continued
10.7 Read Cycle Timing Parameters
(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
Read Cycle Time
Row / Column Address Set Up Time
Row / Column Address Hold Time
Address Access Time
Output Enable Access Time
#OE Low to Active Output
#OE High to High-Z Output
Output Hold from Address Change
TRC
TAS
TAH
TAA
TOE
TOLZ
TOHZ
TOH
W39V040FB
MIN.
MAX.
350
-
50
-
50
-
-
150
-
75
0
-
-
35
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
10.8 Write Cycle Timing Parameters
PARAMETER
Reset Time
Address Setup Time
Address Hold Time
R/#C to Write Enable High Time
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
#OE Hold Time
Byte programming Time
Sector Erase Cycle Time (Note 2)
Program/Erase Valid to RY/#BY Delay
SYMBOL
TRST
TAS
TAH
TCWH
TWP
TWPH
TDS
TDH
TOEH
TBP
TPEC
TBUSY
MIN.
1
50
50
50
100
100
50
50
0
-
-
90
TYP.
-
-
-
-
-
-
-
-
-
12
0.6
-
MAX.
-
-
-
-
-
-
-
-
-
200
6
-
UNIT
μS
nS
nS
nS
nS
nS
nS
nS
nS
μS
S
nS
Notes: 1. All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
2. Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm,
all bytes are programmed to 00H before erasure
10.9 Data Polling and Toggle Bit Timing Parameters
PARAMETER
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
Toggle or Polling interval
SYMBOL
TOEP
TOET
-
W39V040FB
MIN.
MAX.
-
350
-
350
50
-
UNIT
nS
nS
mS
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Publication Release Date: December 12, 2005
Revision A4