W39V040FB_07 Datasheet, PDF (11/34 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V040FB
8. TABLE OF OPERATING MODES
8.1 Operating Mode Selection - Programmer Mode
MODE
Read
Write
Standby
Write Inhibit
Output Disable
#OE
VIL
VIH
X
VIL
X
VIH
#WE
VIH
VIL
X
X
VIH
X
#RESET
VIH
VIH
VIL
VIH
VIH
VIH
PINS
ADDRESS
AIN
AIN
X
X
X
X
DQ.
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
8.2 Operating Mode Selection - FWH Mode
Operation modes in FWH interface mode are determined by "START Cycle" when it is selected.
When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".
8.3 FWH Cycle Definition
FIELD
START
IDSEL
MSIZE
TAR
ADDR
SYNC
DATA
NO. OF
CLOCKS
1
1
1
2
7
N
2
DESCRIPTION
"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle. 0000b" appears on FWH bus to indicate the initial
This one clock field indicates which FWH component is being selected.
Memory Size. There is always show “0000b” for single byte access.
Turned Around Time
Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and
Address[3:0] on FWH[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble
first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then
DQ[7:4] on FWH[3:0] last.)
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Publication Release Date: December 12, 2005
Revision A4