W25Q40BV_12 Datasheet, PDF (2/73 Pages) Winbond – 4M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q40BV
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................... 5
2. FEATURES ....................................................................................................................................... 5
3.
PACKAGE TYPES ............................................................................................................................ 6
3.1 Pin Configuration SOIC /VSOP 150-mil, SOIC 208-mil........................................................ 6
3.2 Pad Configuration WSON 6X5-mm, USON 2X3-mm .......................................................... 6
3.3 Pin Configuration PDIP 300-mil ............................................................................................ 6
3.4 Pin Description SOIC, VSOP, WSON, USON, PDIP ........................................................... 6
4. PIN DESCRIPTIONS ........................................................................................................................ 7
4.1 Chip Select (/CS) .................................................................................................................. 7
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)..................................... 7
4.3 Write Protect (/WP) .............................................................................................................. 7
4.4 HOLD (/HOLD) ..................................................................................................................... 7
4.5 Serial Clock (CLK) ................................................................................................................ 7
5. BLOCK DIAGRAM ............................................................................................................................ 8
6. FUNCTIONAL DESCRIPTION ......................................................................................................... 9
6.1 SPI OPERATIONS ............................................................................................................... 9
6.1.1 Standard SPI Instructions.......................................................................................................9
6.1.2 Dual SPI Instructions ..............................................................................................................9
6.1.3 Quad SPI Instructions.............................................................................................................9
6.1.4 Hold Function .........................................................................................................................9
6.2 WRITE PROTECTION ....................................................................................................... 10
6.2.1 Write Protect Features .........................................................................................................10
7. CONTROL AND STATUS REGISTERS......................................................................................... 11
7.1 STATUS REGISTER .......................................................................................................... 11
7.1.1 BUSY....................................................................................................................................11
7.1.2 Write Enable Latch (WEL)....................................................................................................11
7.1.3 Block Protect Bits (BP2, BP1, BP0)......................................................................................11
7.1.4 Top/Bottom Block Protect (TB) .............................................................................................11
7.1.5 Sector/Block Protect (SEC) ..................................................................................................11
7.1.6 Complement Protect (CMP)..................................................................................................12
7.1.7 Status Register Protect (SRP1, SRP0).................................................................................12
7.1.8 Erase/Program Suspend Status (SUS) ................................................................................12
7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................12
7.1.10 Quad Enable (QE) ..............................................................................................................13
7.1.11 Status Register Memory Protection (CMP = 0)...................................................................14
7.1.12 Status Register Memory Protection (CMP = 1)...................................................................15
7.2 INSTRUCTIONS................................................................................................................. 16
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