W39L010 Datasheet, PDF (19/27 Pages) Winbond – 128K X 8 CMOS FLASH MEMORY

W39L010
AC Characteristics, continued
8.6 Read Cycle Timing Parameters
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
#CE Low to Active Output
#OE Low to Active Output
#CE High to High-Z Output
#OE High to High-Z Output
Output Hold from Address Change
TRC
TCE
TAA
TOE
TCLZ
TOLZ
TCHZ
TOHZ
TOH
W39L010-70
MIN. MAX.
70
-
-
70
-
70
-
35
0
-
0
-
-
25
-
25
0
-
W39L010-90
MIN. MAX.
90
-
-
90
-
90
-
45
0
-
0
-
-
25
-
25
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
8.7 Write Cycle Timing Parameters
PARAMETER
Address Setup Time
Address Hold Time
#WE and #CE Setup Time
#WE and #CE Hold Time
#CE High Setup Time
#OE High Hold Time
#CE Pulse Width
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
Byte Programming Time
Chip Erase Cycle Time
Page Erase Cycle Time
SYM.
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
TDH
TBP
TEC
TEP
MIN.
0
40
0
0
0
0
100
100
100
40
10
-
-
-
TYP.
-
-
-
-
-
-
-
-
-
-
-
35
150
12.5
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
MAX.
-
-
-
-
-
-
-
-
-
-
-
50
200
25
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
mS
mS
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Publication Release Date: January 9, 2004
Revision A4