W83194BR-903 Datasheet, PDF (18/26 Pages) Winbond – STEPLESS VIA PT/PM MAIN CLOCK GENERATOR

W83194BR-903
7.19 Register 18: Slew rate Control (Default: 00h)
BIT
NAME
PWD
DESCRIPTION
7 PCI_65_S2 0 PCI6, 5 slew rate control
6 PCI_65_S1 0 11: Strong, 00: Weak, 10/01: Normal
5 PCI_42_S2 0 PCI4, 3,2 slew rate control
4 PCI_42_S1 0 11: Strong, 00: Weak, 10/01: Normal
3 PCI_10_S2 0 PCI1, 0 slew rate control
2 PCI_10_S1 0 11: Strong, 00: Weak, 10/01: Normal
1
REF_S2
0 REF0, 1 slew rate control
0
REF_S1
0 11: Strong, 00: Weak, 10/01: Normal
7.20 Register 19: Slew rate Control (Default: D2h)
BIT
NAME
PWD
DESCRIPTION
7 CPU1STOP_EN 1 Stop CPU1 clocks, 1: Enable stop feature, 0: Disable
6 CPU0STOP_EN 1 Stop CPU0 clocks, 1: Enable stop feature, 0: Disable
5
25MHz_S2
0 25MHz_1, 0 slew rate control
4
25MHz_S1
1 11: Strong, 00: Weak, 10/01: Normal
Invert the 48MHz phase, 0: In phase with 24_48MHz
3 INV_48MHz 0
1: 180 degrees out of phase
2
48MHz_S2
0 48MHz/24_48MHz slew rate control
1
48MHz_S1
1 11: Strong, 00: Weak, 10/01: Normal
Pin 19,20 Mode selection
1: PCI_STOP, CPU_STOP Control pin
0
MODE
X
0: PCI5, PCI6 (Default)
Default value follow hardware trapping data on MODE^&/PCI0 pin.
7.21 Register 20: Watch dog timer (Default: 08h)
BIT
NAME
PWD
DESCRIPTION
7
SRCF1
0
SRC frequency select, 00/01: 25MHz(Default), 10: 100mhZ, 11:
200MHz
6 WD_TIME [6] 0 _{Setting the down count depth. One bit resolution represents 250ms.}
5 WD_TIME [5] 0 Default time depth is 8*250ms = 2.0 second. If the watchdog timer is
4 WD_TIME [4] 0 ^{counting, this register will return present down count value}
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