W83194BR-903 Datasheet, PDF (16/26 Pages) Winbond – STEPLESS VIA PT/PM MAIN CLOCK GENERATOR

W83194BR-903
Table-2 CPU, AGP, PCI divider ratio selection Table
AGP
CPU
LSB
MSB
Bit5
0
1
Bit1, 0
00
01
10
Bit2/ 0 Div6
Div7
Div2 Div3 Div4
Bit9 1 Div10 Div12 Div8 Div8 Div8
11
Div6
Div8
7.14 Register 13: Divisor and Step-less Enable Control (Default: 0Fh)
BIT
NAME
PWD
DESCRIPTION
0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
7 EN_MN_PROG 0
VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be clear. Then the
frequency will be decided by hardware default FS<4:0> or desired
frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0
- bit 0).
6
Reserved
0 Reserved
5
Reserved
0 Reserved
4
Reserved
0 Reserved
3
IVAL<3>
1
2
IVAL<2>
1
Charge pump current selection
1
IVAL<1>
1
0
IVAL<0>
1
7.15 Register 14: Control (Default: 0Ah)
BIT
NAME
PWD
DESCRIPTION
CPUT output state in during POWER DOWN or Stop mode assertion.
1: Driven (2*Iref),
7 CPUT_DRI 0
0: Tristate (Floating)
CPUC always tri-state (floating) in power down Assertion.
6
Reserved
0 Reserved
5
SPCNT [5]
0
4
SPCNT [4]
0
3
SPCNT [3]
1 _{Spread Spectrum Programmable time, the resolution is 280ns. Default}
2
SPCNT [2]
0 ^{period is 11.8us}
1
SPCNT [1]
1
0
SPCNT [0]
0
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