W83194R-39 Datasheet, PDF (17/21 Pages) Winbond – 100MHZ 3-DIMM CLOCK

W83194R-39/-39A
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
1
2
3
4
PRELIMINARY
1
2
3
4
CPUCLK[0:3]
SDRAM
For synchronous Chipset, CPU_STOP# pin is an asynchronous “ active low ” input pin used to stop
the CPU clocks for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU “clocks on latency“ is less than 4 CPU clocks and
“clocks off latency” is less then 4 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
1
2
1
2
PCI_STOP#
PCICLK[0:5]
For synchronous Chipset, PCI_STOP# pin is an asynchronous “active low” input pin used to stop
the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control
logic at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run
while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume
output with full pulse width. In this case, PCI “clocks on latency“ is less than 2 PCI clocks and
“clocks off latency” is less then 2 PCI clocks.
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Publication Release Date: May 1998
Revision 0.20