W19B160BTT7H Datasheet, PDF (14/47 Pages) Winbond – 2.7~3.6-volt write (program and erase) operations, Fast write operation

W19B160BT/B DATA SHEET
As the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. Please refer to the Write Operation Status section for information on
these status bits.
However, a hardware reset shall terminate the erase operation immediately. If this occurs, to ensure
data integrity, the sector erase command sequence should be reinitiated once the device has returned
to reading array data.
6.2.7 Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than
using the standard program command sequence. The unlock bypass command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass
command, 20h. The device enters the unlock bypass command mode. A two-cycle unlock bypass
program command sequence is all that is required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Command Definitions shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-pass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Program/Erase operation refer Program Algorithm and Erase Algorithm illustration.
6.3 WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6,
and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase
operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY,
to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1 DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in
progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the
command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. When the Embedded Program algorithm is complete, the device outputs the
data programmed to DQ7. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is
active for about 1µS, and then the device returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7.Once the Embedded
Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the
sectors selected for erasure must be provided to read valid status information on DQ7.
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