W49F102 Datasheet, PDF (13/21 Pages) Winbond – 64K X 16 CMOS FLASH MEMORY

W49F102
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5.0V ±5 % for 35 nS; VDD = 5.0V ±10 % for 40/45 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
W49F102-40
MIN.
MAX.
W49F102-45
MIN.
MAX.
Read Cycle Time
Chip Enable Access Time
TRC
42
-
45
-
TCE
-
40
-
45
Address Access Time
TAA
-
40
-
45
Output Enable Access Time
TOE
-
20
-
25
CE Low to Active Output
TCLZ
0
-
0
-
OE Low to Active Output
TOLZ
0
-
0
-
CE High to High-Z Output
TCHZ
-
15
-
20
OE High to High-Z Output
TOHZ
-
15
-
20
Output Hold from Address
TOH
0
-
0
-
Change
Write Cycle Timing Parameters
PARAMETER
Address Setup Time
Address Hold Time
WE and CE Setup Time
WE and CE Hold Time
OE High Setup Time
OE High Hold Time
CE Pulse Width
CE High Width
WE Pulse Width
WE High Width
Data Setup Time
Data Hold Time
Word Programming Time
Erase Cycle Time
SYMBOL
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TCPH
TWP
TWPH
TDS
TDH
TBP
TEC
MIN.
0
45
0
0
0
0
50
50
45
45
45
0
-
-
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
10
0.1
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
MAX.
-
-
-
-
-
-
-
-
-
-
-
-
50
1
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
Sec.
- 13 -
Publication Release Date: October 2000
Revision A3