W83301R Datasheet, PDF (11/16 Pages) Winbond – ACPI-STR Controller

W83301R
Preliminary
7.3 Charge Pump
In order to simply the design circuit and provide a good-price solution for customer,
the W83301R integrate with a switched-capacitor voltage doubler charge pump to
provide a higher driving voltage (Up to 10 volt) and can drive a single N-channel
MOSFETs in each output.
7.4 Power OK
The W83301R use a bi-direction Power OK signal to ensure the system can work
normally. When the system jump from state S3 to state S0, the W83301R will monitor the
input signal from PWOK pin to ensure that external system power is OK and then switch
each outputs into S0 stage; In the other hand, the W83301R will pull down the Power OK
signal to inform the system that a over current and induce under-voltage occurred.
7.5 Soft-Start
During ‘S5off’ to ‘S5on’ and ‘S5on’ to ‘S0’ state transitions, the 5Vdual and STR
voltages need to ramp up from 0 to their set values respectively. The charging current
flowing to output capacitors must be limited to avoid supply drop-off.
In W83301R, an internal 18 uA current source (Iss) charges an external capacitor
(Css) to generate a linear ramp-up voltage on SS pin (Vss). The Vss slews from 0 to
about 9V during the above-mentioned state transitions, and the Vss slew rate is used to
clamp the ramp-up rate of 5Vdual and STR output voltages. This output clamping allows
power-ups free of supply drop-off events.
Since the outputs are ramped up in a constant slew-rate, the current dedicated to
charge any output capacitor can be calculated with the following formula:
I_COUT = Iss x (Cout / Css)
Some technique is included in W83301R to further reduce the total charging current:
In Mode B configuration, the start-up of ramp-up time STR3 (1.8V) will be advanced from
that of STR1 to reduce the overlap time of charging. And in Mode A configuration, the
bus-terminator is input clamped, and its output voltage slew-rate, so as its charging
current, will be limited to half of that of STR1.
Note that, too slow ramp-up rate is not recommended. If so, the state transition
mentioned above will be prolonged to much. Before Vss ramps up to its upper limit
(about 9V), the state transition will not be completed and will not go into next state.
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Revision 0.6