W29C011A Datasheet, PDF (11/19 Pages) Winbond – 128K X 8 CMOS FLASH MEMORY

Preliminary W29C011A
Read Cycle Timing Parameters
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address change
TRC
TCE
TAA
TOE
TCLZ
TOLZ
TCHZ
TOHZ
TOH
W29C011A-15
MIN.
MAX.
150
-
-
150
-
150
-
70
0
-
0
-
-
45
-
45
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
Byte/Page-Write Cycle Timing Parameters
PARAMETER
Write Cycle (erase and program)
Address Setup Time
Address Hold Time
WE and CE Setup Time
WE and CE Hold Time
OE High Setup Time
OE High Hold Time
CE Pulse Width
WE Pulse Width
WE High Width
Data Setup Time
Data Hold Time
Byte Load Cycle Time
Byte Load Cycle Time-out
SYMBOL
TWC
TAS
TAH
TCS
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
TDH
TBLC
TBLCO
MIN.
-
0
50
0
0
10
10
70
70
150
50
10
0.22
300
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
MAX.
10
-
-
-
-
-
-
-
-
-
-
-
200
-
UNIT
mS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
µS
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Publication Release Date: December 1997
Revision A1