WCMA2016U4B Datasheet, PDF (6/12 Pages) Weida Semiconductor, Inc. – 128K x 16 Static RAM

WCMA2016U4B
Switching Waveforms
Read Cycle No. 1 (Address Transistion Controlled) ^{[13, 14]}
t_RC
ADDRESS
t_AA
t_OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) ^{[14, 15]}
ADDRESS
CE
OE
BHE/BLE
t_RC
t_ACE
t_DOE
tt_LLZZOOEE
DATA OUT
V_CC
SUPPLY
CURRENT
t_DBE
t_LZBE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
DATA VALID
t_PD
t_HZCE
t_HZOE
t_HZBE
HIGH
IMPEDANCE
I_CC
50%
I_SB
Notes:
13. Device is continuously selected. OE, CE = V_IL, BHE, BLE = V_IL.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident withCE, BHE, BLE transition LOW.
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