WCMA2016U4B Datasheet, PDF (5/12 Pages) Weida Semiconductor, Inc. – 128K x 16 Static RAM

WCMA2016U4B
Switching Characteristics Over the Operating Range^[8]
55ns
70 ns
Parameter
Description
Min
Max
Min
Max
Unit
READ CYCLE
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t
[10]
LZBE
t_HZBE
WRITE CYCLE^[12]
Read Cycle Time
55
70
ns
Address to Data Valid
55
70
ns
Data Hold from Address Change
10
10
ns
CE LOW to Data Valid
55
70
ns
OE LOW to Data Valid
OE LOW to Low Z^[9]
OE HIGH to High Z^{[9, 11]}
CE LOW to Low Z^[9]
CE HIGH to High Z^{[9, 11]}
25
35
ns
5
5
ns
25
25
ns
10
10
ns
25
25
ns
CE LOW to Power-Up
0
0
ns
CE HIGH to Power-Down
55
70
ns
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z^[9]
BHE / BLE HIGH to High Z^{[9, 11]}
55
70
ns
5
5
ns
25
25
ns
t_WC
Write Cycle Time
55
70
ns
t_SCE
CE LOW to Write End
45
60
ns
t_AW
Address Set-Up to Write End
45
60
ns
t_HA
Address Hold from Write End
0
0
ns
t_SA
Address Set-Up to Write Start
0
0
ns
t_PWE
WE Pulse Width
40
50
ns
t_BW
BHE / BLE Pulse Width
50
60
ns
t_SD
Data Set-Up to Write End
25
30
ns
t_HD
t_HZWE
t_LZWE
Data Hold from Write End
WE LOW to High Z^{[9, 11]}
WE HIGH to Low Z^[9]
0
0
ns
20
25
ns
5
10
ns
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V_CC(typ.) /2, input pulse levels of 0 to V _CC(typ.), and output loading of
the specified I_OL/I_OH and 30 pF load capacitance.
9. At any given temperature and voltage condition, t _HZCE is less than t_LZCE, t_HZBE is less than t_LZBE, t _HZOE is less than t _LZOE, and t _HZWE is less than t_LZWE for
any given device.
10. If both byte enables are toggled together this value is 10ns
11. t_HZOE, t _HZCE, t_HZBE, and t _HZWE transitions are measured when the outputs enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = V_IL , BHE and/or BLE = V _IL. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write..
5